At DAC, Experts Tackle Rising Thermal Challenges in Chip and System Design

During a roundtable at the recent Design Automation Conference (DAC), Semiconductor Engineering brought together experts from Synopsys, Silvaco, Vinci, Keysight, and Siemens (Mentor) to discuss thermal management and thermal-related trade-offs in chip and system design.

The panelists noted that rising power density and growing complexity of chiplets are pushing thermal effects into architectural decisions. Design teams must balance power, performance, reliability, floorplanning, packaging, and cooling. Chiplets and advanced packaging amplify the difficulty of thermal analysis, requiring evaluation of hotspots, crosstalk, material properties, and thermal paths at the package and system level rather than at a single die.

Experts called for more scalable multiphysics modeling, reduced-order models, digital twins, and tightly coupled physics solvers to accurately predict thermal behavior. On the cooling side, thermal interface materials, cold plates, immersion cooling, and direct-on-chip cooling were discussed. One panelist expected immersion and two-phase cooling to be deployed in production in 2026-2027.

Thermal simulation is also moving toward device-level granularity. While IR drop analysis can already reach single-gate resolution, single-gate thermal analysis is not yet mature. The model context protocol (MCP) was cited as a necessary but not sufficient condition for solver coordination and digital-twin-based trade-off analysis.