SK hynix unveils H-TPU architecture to address AI data center storage bottlenecks
On October 12, 2026, Koo In-jae, Vice President of SoC Design at SK hynix, delivered a keynote at ISOCC 2026 in Songdo, Incheon, South Korea, introducing the company's self-developed ultra-lightweight transaction-specific processor architecture, H-TPU. He said AI data centers face structural limitations: while GPU performance and PCIe bandwidth double every generation, the frequency and control capabilities of general-purpose CPUs inside SSD controllers are reaching their limits.
He explained that traditional monolithic CPU architectures struggle to handle the hundreds of fine-grained functions required for storage control, and simply boosting core performance leads to significant power waste and unpredictable pipeline latency. H-TPU is not a tensor accelerator for AI compute, but a programmable processor dedicated to controlling SSD data planes and handling transactions. The design splits control functions into functional units distributed across dozens of small TPU clusters, using a simplified four-stage pipeline without superscalar or out-of-order execution. The H-TPU core occupies about 1/25 the area of a general-purpose CPU core and consumes roughly 2.5% of its power; only function blocks related to specific tasks such as writes are active, while unused blocks switch to a low-power mode.
SK hynix plans to apply H-TPU technology across its NAND memory product lines, including next-generation enterprise SSD (eSSD) controllers, and later use it in the next-generation AI storage architecture "Storage Next". The company expects controller innovations built around H-TPU to create synergy with the new high-bandwidth flash memory "HBF", scheduled for release in 2027.
