Peking University Team Unveils Programmable Optoelectronic AI Inference Chip

At the 19th Pujiang Innovation Forum's Silicon Photonics Development Forum on September 14, 2026, Tao Yaoyu from Peking University's Xinyao Yue team unveiled a programmable spatial optoelectronic heterogeneous AI inference chip.

The chip features a digital light intensity accumulation and multiply-accumulate split short optical path architecture, combined with electro-optic-electro 3D heterogeneous integration and an in-house flow-control compiler. It targets low-error, low-loss, and programmable AI inference acceleration. The team noted that cloud-edge large model inference has placed growing demands on response latency and speed, and photonic computing can help address these bottlenecks.

The architecture was developed to overcome practical engineering challenges such as error accumulation, thermal sensitivity, and optical path attenuation caused by long-path interference and diffraction effects. By adopting large-array optical sources in volume production and electro-optic-electro 3D heterogeneous packaging, the team aims to advance photonic computing from 2D planes to 3D space, enabling low error, low loss, and programmable inputs/weights. Its flow-control compiler, based on reinforcement learning and accounting for non-ideal factors such as bad-point avoidance, is compatible with PyTorch and achieves first-token latency at the hundred-microsecond level, with peak throughput exceeding tens of thousands of tokens per second.

Tao Yaoyu said that while optical computing chips have been actively explored for nearly a decade, the technology has not yet converged. The team intends to tackle latency and speed challenges in cloud-edge large model inference.