Google Expands TPU System to Million-Chip Scale, Cites Power as Key Bottleneck

At SEMICON Taiwan 2026, Google announced that its TPU system has expanded to a million-chip scale, meaning its TPU interconnect architecture can now support connecting up to one million TPU chips into a unified computing cluster for distributed training across multiple data centers and pods.

Google CTO Amin Vahdat said in a keynote that as AI models grow, the core bottleneck has shifted from chips to power supply. He noted that the ceiling for AI computing is no longer about manufacturing chips but about finding electricity. Vahdat also said AI has entered the era of agentic AI, where interactions are moving from human-machine to agent-to-agent automated conversations, driving exponential growth in AI applications and creating nearly unlimited global compute demand.

Google's agreement with Anthropic involves up to one million TPU chips with a total computing power exceeding one gigawatt. Starting in 2027, Google will provide Anthropic with 3.5 to 5 gigawatts of TPU compute capacity in a deal valued at up to $40 billion. Other tech giants face similar power constraints; for instance, Amazon is purchasing an additional two million Nvidia chips for its AI infrastructure, but power shortages have become a common challenge for global AI data center expansion.

In terms of specifications, Google's Ironwood TPU (TPU v7) delivers 4,614 TFLOPS of FP8 compute per chip, with a 9,216-chip pod offering up to 42.5 exaflops of performance. At the Cloud Next conference in April 2026, Google unveiled its eighth-generation TPUs, including the training-focused TPU 8t and inference-focused TPU 8i, with the TPU 8t superpod scaling to 9,600 chips.