Huawei Unveils Peerium Architecture and UnifiedBus for AI Computing

At the 2026 Huawei Connect conference, Huawei's rotating chairman Xu Zhijun and chief scientist of semiconductors Liao Heng discussed the progress of the Ascend chip roadmap and introduced the newly released Peerium computing architecture and the UnifiedBus (Lingqu) interconnect technology.

According to Xu, the Ascend 950 chip is now available, the Atlas 950 supernode has begun delivery, a 256,000-card cluster based on it is being deployed, and the next-generation Atlas 960 system is in testing. Huawei also unveiled the Ascend 960 supernode, described as the world's first to adopt near-package optics (NPO) technology.

The Peerium architecture is designed to support collaboration among millions of processors through nested parallelism, unified memory addressing, and equal interconnect. UnifiedBus aims to extend bus protocols beyond chassis to inter-cabinet and data-center-wide connections, reducing overhead from protocol conversions. Huawei says the combination can significantly improve model floating-point utilization (MFU).

Xu said the choice of NPO over co-packaged optics (CPO) was a balanced decision considering engineering, cost, supply chain division and maintenance, bringing about a nearly 40% cost reduction while allowing relatively independent maintenance of optical engines. Huawei plans to open the UB protocol to encourage ecosystem development.

For supply, the training-oriented Ascend 950DT is expected to ship in scale by late 2026 or 2027. Xu predicted that from 2027, a large number of model training workloads will run on supernodes or clusters based on 950DT.