Chip designer Mr. Bubble: Advanced packaging is the new Moore's law, Nvidia roadmap limited by memory and packaging

On September 22, 2026, chip designer Mr. Bubble said in an interview on the Frictionless Podcast that the real bottlenecks in AI compute infrastructure have shifted from chips to advanced packaging, interconnect latency, and memory hierarchy. He argued that Moore's law is economically broken and that advanced packaging has become the new Moore's law.

Mr. Bubble cited Nvidia's roadmap as an example: Rubin Ultra was originally planned with four dies in one package but was reportedly downgraded to two dies per package with two packages connected via PCB, making PCB makers a new bottleneck. He said he had been bullish on Intel due to its EMIB packaging technology, but that the bigger opportunity may be in PCB manufacturers.

On the inference side, he said prefill-decode disaggregation is becoming mainstream, citing Kimi's reference design. He suggested flash offload and high-bandwidth flash (HBF) can handle massive contexts instead of relying solely on HBM, and predicted 3D DRAM as the ultimate memory form, with DRAM bonded directly over logic to reduce latency and power while increasing bandwidth.

He also questioned the "pacing the frontier" narrative from large model labs, noting they have not paused data center construction or cut capital expenditures. He said he prefers owning hardware-layer companies and believes five to ten new drugs discovered with AI could justify all AI capex.