Qualcomm Brings HBC Architecture to Snapdragon Chips to Address AI Inference Memory Bottleneck

At the 2026 Snapdragon Summit in Hawaii on September 22, Qualcomm announced it will bring its High Bandwidth Compute (HBC) architecture to Snapdragon chips. The architecture, first unveiled at an investor day in June 2026 and originally aimed at data center products, will now be extended to mobile processors.

HBC is a near-memory computing architecture that places the compute die beneath stacked LPDDR DRAM and uses 3D integration and through-silicon vias (TSVs) to shorten data paths between compute and memory. It targets the “memory wall” problem in AI inference, which refers to the bottleneck caused by moving model parameters and intermediate data between memory and processor.

By moving some compute closer to memory, HBC reduces data movement, potentially lowering latency and memory power consumption. For end users, Snapdragon-powered phones could run larger on-device AI models faster and more efficiently, as well as enable more AI features locally. If HBC also improves effective bandwidth and performance-per-watt, phones may be able to handle models with more parameters and longer contexts.

The current limit on on-device AI is no longer just the NPU’s multiply-accumulate capability; the speed of data transfer between memory and processor is equally important. Extending HBC to Snapdragon chips could lead to noticeable improvements in on-device AI experiences.