Resolight.ai applauded the CPO specifications released by the Advanced Photonics Coalition (APC) at the Optica + APC PECC Summit, which aim to enable native photon routing through nanosecond optical circuit switching (OCS). The company says its architecture targets up to 40x better network energy efficiency and 75% fewer optical transceivers in multi-rack AI scale-up networks to improve AI workload economics.
At Six Five Summit 2026, Marvell executives said inference models drove KV cache to expand roughly 10x in nine months, pushing copper interconnect to performance limits and making optical interconnect and memory expansion core variables for compute scaling. Marvell is advancing NPO and CPO paths, analog SerDes can cut power by ~4x, and it introduced a photonic fabric memory device with a 32TB external memory pool; CXL products have seen considerable demand.
Shanghai Sailer Optoelectronics unveiled a single-wavelength 400G silicon photonic chip based on a pure silicon solution at the Pujiang Innovation Forum, targeting next-generation high-speed optical communication. Founder Gan Fuan said the chip is key to moving CPO from the lab to commercial use and will enable CPO to enter hyperscale AI data centers.